By Michel Cosnard (auth.), Ricardo Corrêa, Inês Dutra, Mario Fiallos, Fernando Gomes (eds.)

Parallel and disbursed computation has been gaining an excellent lot of realization within the final many years. in this interval, the advances attained in computing and communique applied sciences, and the relief within the expenditures of these technolo gies, performed a imperative function within the quick development of the curiosity within the use of parallel and allotted computation in a few parts of engineering and sciences. Many real functions were effectively carried out in a number of plat varieties various from natural shared-memory to completely dispensed versions, passing via hybrid techniques resembling distributed-shared reminiscence architectures. Parallel and disbursed computation differs from dassical sequential compu tation in a few of the following significant points: the variety of processing devices, self sustaining neighborhood dock for every unit, the variety of reminiscence devices, and the programming version. For representing this variety, and counting on what point we're taking a look at the matter, researchers have proposed a few versions to summary the most features or parameters (physical elements or logical mechanisms) of parallel desktops. the matter of creating an appropriate version is to discover an affordable trade-off between simplicity, energy of expression and universality. Then, have the capacity to examine and examine extra exactly the habit of parallel applications.

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**Sample text**

It follows that differences in power betwen the models will be hidden by the notation O. This is not the case if the inteconnection netwok is a graph whose degree is a non-constant function of the number of processors. We shall consider a hypercube for the sake of simplicity. 35 A HypercubeRAM or H RAM is a D RAM with a hypercube interconnection network: Xi = H i = {j I binary expansions of i and j differ only on one bit }. Before going to generalize theorems for differentiating and simulating P RAM, we shalllook in a little more detail at the H RAM model by describing an algorithm for the prefix computation.

The minimum number of processors required to solve the problem in optimal time will be called Popt. U sing one processor topt (1) is the sequential complexity of the problem. The theorem on speedup limitations implies that the upper bound of the product p. topt (P), called the cost of the algorithm, is topt (1). Where the cost of a parallel algorithm is the same as that of an optimal sequential algorithm, the parallel algorithm is said to be cost optimal. Fine granularity is the term used if the number of processors is of the same order as the number of data items.

18 Let A ~ {O, I} *. For any given n, we define the circuit (resp. depth) complexity of A at length n as the boolean cost (resp. depth) of the caracteristic function In of An {O, 1 }n. Observe that as functions of n both c(A) and d(A) only depend on A. Correspondingly, if we consider the function family associated to A and caII it In we can generalize the notion of cost and depth. The next theorem relates time and space complexity of a Turing machine computation to size and depth complexity. 19 (TM Simulation by BG [2]) If In is computed in T(n) and S(n) bya Turing machine, then it can be computed in G(T 2) and D(S2) bya boolean circuit.