By David Robert Stauffer, Jeanne Trinko Mechler, Michael A. Sorna, Kent Dramstad, Clarence Rosser Ogilvie, Amanullah Mohammad, James Donald Rockrohr
High pace Serdes units and Applications presents a extensive knowing of excessive velocity Serdes (HSS) equipment utilization. the cloth makes a speciality of HSS units, and the consolidation of comparable subject matters right into a unmarried textual content. Chip and procedure designers utilizing HSS units should have designated wisdom of either the gains and capabilities of the HSS machine, and the functions during which they're used. additionally designers should have a operating wisdom of similar topics, together with: reference clock architectures, sign integrity, strength dissipation, and try good points and features. The authors consolidate those issues with a selected specialise in HSS units. This technique presents the chip clothier enough heritage info for utilizing HSS units on their chips.
The chapters will be seen as 4 special sections. the 1st part pertains to the gains, services, and layout of HSS units. moment are chapters that describe the positive aspects and services of protocol common sense used to enforce a variety of community protocol interface criteria. The 3rd part covers really good issues relating to HSS cores. eventually, features of regular layout package types to facilitate integration in the chip layout are discussed.
High velocity Serdes units and Applications is an invaluable source for chip designers utilizing HSS units of their chip design.
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Extra resources for High Speed Serdes Devices and Applications
1=reset, 0=normal operation HSSRESYNCCLKIN In This input is pulsed to cause a resync to occur. Pulse must be synchronous to HSSRESYNCCLKOUT pin. 0=normal, 1=resync. Multiple core resynchronization requires HSSREFDIV = 0 HSSPLLLOCK Out PLL locked indicator. 0=unlocked, 1=locked HSSRESETOUT Out This signal is asserted high during the VCO coarse calibration and during the beginning of the reset sequence. 1 HSS EX10 PLL slice core pin definitions Pin name Type Description HSSRESYNCCLKOUT Out This clock output is used to synchronize the HSSRESYNCCLKIN signal HSSPRTWRITE In Parallel Port Write.
0=normal, 1=reset 5 R/W 0 Link reset to TXD. 0=normal, 1=reset 6 R/W 0 Link reset to RXC. 0=normal, 1=reset 7 R/W 0 Link reset to RXD. 6 HSS EX10 transmitter slice register definitions Reset value Addr (3:0) Bits R/W 0x1 16 R/W 2:0 R/W 000 3 R/W 0 Test Pattern Generator Enable 0=disable generator and select Customer Parallel Data (default), 1=enable generator and select Test Pattern Data 4 R/W 0 PRBS Reset. 0=normal (default), 1=reset applied to Test Pattern generator 15:5 R 16 R/W 0 R/W 0 Apply Load This bit applies the register-loaded values of coefficients, power, polarity and FFE mode to the coefficient recalculation logic, and presents this new value to the analog circuits 1 R/W 0 Reset Coefficient Logic 0=normal (default), 1=reset 15:2 R 0x2 Description 0x0000 Transmit Test Control Register Note: TXxPRBSEN pin = “1” overrides this register and forces PRBS7+ to be transmitted Test Pattern Selector 000 = PRBS7+ (noninverted) (default) 001 = PRBS7− (inverted) 010 = PRBS23+ (noninverted) 011 = PRBS23– (inverted) 100 = PRBS31+ (noninverted) 101 = PRBS31– (inverted) 110 = 1010101....
Total Jitter (TJ). This is the total jitter of the signal as seen at the point of measurement. TJ can be measured directly on hardware and is the ideal bit time minus the actual eye width, specified as either a peak or peak-to-peak value. 2. Deterministic Jitter (DJ). This is the amount of the total jitter for which the jitter distribution is non-Gaussian. Several components of DJ are dependent on the data pattern being sent. The pattern of 1’s and 0’s which precedes the bit transition affects when the transition occurs.