Logic

Field Programmable Logic and Application: 13th International by Steve Ferrera, Nicholas P. Carter (auth.), Peter Y. K.

By Steve Ferrera, Nicholas P. Carter (auth.), Peter Y. K. Cheung, George A. Constantinides (eds.)

This booklet comprises the papers provided on the thirteenth overseas Workshop on box Programmable common sense and functions (FPL) hung on September 1–3, 2003. The convention was once hosted via the Institute for structures and machine Engineering-Research and improvement of Lisbon (INESC-ID) and the Depa- ment of electric and computing device Engineering of the IST-Technical college of Lisbon, Portugal. The FPL sequence of meetings used to be based in 1991 at Oxford college (UK), and has been held each year due to the fact: in Oxford (3 times), Vienna, Prague, Darmstadt,London,Tallinn,Glasgow,Villach,BelfastandMontpellier.Itbrings jointly educational researchers, commercial specialists, clients and novices in an - formal,welcomingatmospherethatencouragesproductiveexchangeofideasand wisdom among delegates. interesting advances in ?eld programmable common sense exhibit no signal of slowing down. New grounds were damaged in architectures, layout strategies, run-time - con?guration, and functions of ?eld programmable units in different di?erent components. lots of those recommendations are suggested during this quantity. the scale of FPL meetings has grown signi?cantly through the years. FPL in 2002 observed 214 papers submitted, representing a rise of eighty three% when put next to the yr earlier than. The curiosity and aid for FPL within the programmable common sense group persevered this 12 months with 216 papers submitted. The technical p- gram was once assembled from ninety chosen usual papers and fifty six posters, leading to this quantity of complaints. this system additionally integrated 3 invited plenary keynote shows from LSI good judgment, Xilinx and Cadence, and 3 commercial tutorials from Altera, Mentor photos and Dafca.

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Extra resources for Field Programmable Logic and Application: 13th International Conference, FPL 2003, Lisbon, Portugal, September 1-3, 2003 Proceedings

Sample text

Each cell only accepts two signals to generate a logic function. Then at least two output-drivers and the redirection multiplexers in its neighbor cells can be turned off to save power. If the input signal of a cell is selected from FastLANE, all four output-drivers in all neighbor cells can be turned off to save power. 3. When a cell is only used to redirect a signal from one neighbor cell to another neighbor cell, the function unit of the cell may be turned off to save power. Dynamic Routing Circuits Dynamic routing circuits are used to turn off CML trees and the whole basic cell.

With the advent of 90 nm and beyond processes, application specific integrated circuits (ASICs) are becoming too expensive to miss a single market. Due to this fact, field-programmable gate arrays (FPGAs) are the hardware platform of choice for SDR: FPGAs can quickly be adapted to new emerging standards or to cope with the last minute changes of the specifications. In particular, this work will focus on a certain subset of FPGA architectures: look-up table (LUT)-based FPGAs. We have targeted commercial devices belonging to this set: Xilinx Virtex-II Pro.

Cheung et al. ): FPL 2003, LNCS 2778, pp. 11–20, 2003.  Springer-Verlag Berlin Heidelberg 2003 12 C. You et al. The layout of the paper is this. Section 2 introduces the SiGe BiCMOS technology. 4 V to 2 V. Section 4 presents an improved basic cell structure that eliminates redundant multiplexing procedures and thus increases performance. Section 5 illustrates the dynamic routing circuits that shut down unused circuits. Section 6 presents the concept of the 3-D FPGA aiming at reducing the area and the influence of parasitic effects.

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