Microelectronics

Embedded software for SOC by Ahmed A Jerraya; et al

By Ahmed A Jerraya; et al

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It is also possible to determine the available headroom above the calculated worst case‚ to estimate how much additional functionality could be integrated without violating timing constraints. In the following we demonstrate that formal analysis is consistently applicable for single processes‚ RTOS overhead‚ and single ECUs‚ and give an outlook on networked ECUs‚ thus opening the door to formal timing analysis for the certification of automotive software. 1. Single process analysis Formal single process timing analysis determines the worst and best case execution time (WCET‚ BCET) of one activation of a single process assuming an exclusive resource.

SOFTWARE INTEGRATION In this section‚ we address the roles and functional issues proposed in Figure 2-1 for a safe software integration flow‚ in particular RTOS configuration‚ communication conventions and memory budgeting. The functional software structure introduced in this section also helps to better understand performance issues which are discussed in Section 5. 1. RTOS configuration In an engine ECU‚ most tasks are either executed periodically‚ or run synchronously with engine RPM. RTOS configuration (Figure 2-1) includes setting the number of available priorities‚ timer periods for periodic tasks etc.

This is done using a spin lock‚ whose implementation depends on the architecture. A spin lock is acquired using the pthread_spin_lock function‚ Chapter 3 28 and released using pthread_spin_unlock. Our implementation assumes that there is a very basic binary semaphore engine in uncached space such that reading a slot in it returns the value of the slots and sets it to 1. Writing in a slot sets it to 0. Other strategies can make use of the read modify write opcode of the VCI standard‚ but this is less efficient and requires that each target is capable of locking its own access to a given initiator‚ thus requiring more resources per target.

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