By Dr. Ron Ho, Dr. Robert Drost (auth.), Ron Ho, Robert Drost (eds.)
Designers of next-generation high-performance desktops face a bunch of technical demanding situations. For the previous a number of many years, emerging clock frequencies and elevated chip integration have fueled the expansion of computing device functionality. Now those developments have slowed: strength and complexity constrains extra raises in clock frequencies, and fiscal realities restrict the speed of Moore's legislation. Coupled info verbal exchange presents a fashion ahead, and this e-book, Coupled information communique suggestions for High-Performance and Low-Power Computing, offers a entire assessment for such coupled information recommendations. Coupled facts communique permits chips to communicate—capacitively or inductively—over brief distances among chips with out solder, and essentially shifts the layout paradigm from single-chip integration to single-package integration. This e-book covers the cutting-edge within the circuits, architectures, and chip packaging for this novel chip-to-chip communique expertise and showcases its power to force the arriving many years of progress. Coupled info conversation ideas for High-Performance and Low-Power Computing may be of curiosity to scholars and architects in circuits and process architecture.
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Additional info for Coupled Data Communication Techniques for High-Performance and Low-Power Computing
6 Schematic illustration of a chip with electrical, optical, and fluidic (“trimodal”) I/O interconnects. Electrical chip I/O interconnection is achieved using solder bumps. The optical I/Os are implemented using surface-normal optical waveguides and take the form of polymer pins [25, 26, 27]. A polymer pin, like a fiber optic cable, consists of a waveguide core and a cladding. The polymer pin acts as the waveguide core, and unlike a fiber optic cable, the cladding is air. A key feature of the optical pins is that they are mechanically flexible and thus, can bend to compensate for the coefficient of thermal expansion (CTE) mismatch between the chip and substrate.
Unlike prior work on microfluidic cooling of ICs that require millimeter-sized and bulky fluidic inlets/outlets to the microchannel heat sink, the micropipe I/Os under consideration are microscale, wafer-level batch fabricated, area-array distributed, flip-chip compatible, and mechanically compliant. 8 illustrates the evolution of thermal interconnects, including the thermal interconnects under consideration. This is discussed in Section . 2 2D and 3D integrated systems 19 Cap Optical device Si 100 m 200 m Microchannel heat sink Fluidic I/O Cu pad Optical pin I/O Solder bump Optical waveguide Fluidic channel Optical & Fluidic I/Os Electrical & Optical I/Os Electrical & Fluidic I/Os Fig.
In the “bending” case, the controlled lateral displacement of the light source causes the optical pin to bend sideways helping to keep the lightmode confined in the pin and thus deliver the optical signal to the detector with lower coupling losses. 17. The loss reduction is less than 1 dB up to 15 µm displacement, while it increases up to 4 dB at 30 µm. This is significant since a limited loss budget is available in typical systems for misalignments/assembly to maintain proper operation. , 1 dB, the 50x150 µm flexible pins double the displacement tolerance from less than 15 µm to approximately 30 µm.