Microelectronics

Analog Circuit Design Techniques at 0.5 V by Shouri Chatterjee, K.P. Pun, Nebojša Stanic, Yannis

By Shouri Chatterjee, K.P. Pun, Nebojša Stanic, Yannis Tsividis, Peter Kinget

Analog layout at ultra-low offer voltages is a vital problem for the semiconductor examine group and industry.

Analog Circuit layout ideas at 0.5V covers demanding situations for the layout of MOS analog and RF circuits at a 0.5V energy provide voltage. All layout recommendations awarded are actual low voltage innovations - all nodes within the circuits are in the strength provide rails. The circuit implementations of physique and gate enter totally differential amplifiers also are mentioned. those construction blocks allow us to construct continuous-time filters, track-and-hold circuits, and continuous-time sigma delta modulators.

Current books on low voltage analog layout ordinarily hide thoughts for provide voltages right down to nearly 1V. This ebook provides novel principles and effects for operation from a lot decrease offer voltages and the suggestions provided are simple circuit concepts which are extensively acceptable past the scope of the awarded examples.

Analog Circuit layout innovations at 0.5V is written for analog circuit designers and researchers in addition to graduate scholars learning semiconductors and built-in circuit design.

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Extra info for Analog Circuit Design Techniques at 0.5 V

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27: Harmonic distortion in the gate-input OTA, in closed loop, for different input amplitudes. 18 Lat. Lat. Depl. 4 GBW · CL Isupply A basic input stage of a gate-input OTA, as shown earlier in Fig. 8(b), but without the common-mode feed-forward structures, is shown in Fig. 28(a). An extension of this OTA stage, that takes full advantage of low-VT devices, and does not require access to the bodies of the devices, is shown in Fig. 28(b). The devices M1A and M1B in Fig. 28(a) are each replaced with two devices – M1A is replaced with a combination of M11A and M12A , and M1B is replaced with a combination of M11B and M12B .

However, this is satisfactory for the input stage. 25 V). This enables maximum output swing. The bias voltages at all the nodes in the circuit are indicated. 7 Summary 45 common-mode feed-forward circuitry in Fig. 8(b) can be included to improve the common-mode rejection of this OTA input stage. 2 Bias circuits The switching threshold voltage of the error amplifiers discussed in Fig. 12 are controlled by the voltage Vamp . This voltage, applied to the body of the nMOS device in the error amplifier, controls the threshold voltage of the nMOS devices in each error amplifier.

This in turn will result in larger capacitances that the circuit will need to drive. 5 µm was chosen for all devices in this circuit as a compromise in the trade-off between lower VT , larger area requirements, and larger parasitic capacitance. Currents of 40 µA and 4 µA were input through the nodes “biasn” and “biasi” as in Fig. 5. The current mirrors reflect these currents through M2A , M2B and M4 respectively. 22 2 Fully Differential Operational Transconductance Amplifiers (OTAs) biasi M4 VDD biasn M2 Vin+ M1A M2A M3A RA RB M4 M3B M1B M2B Vin- R C CC VoutM1A’ M3A’ M2A’ CL RA’ RB’ M4’ M3B’ CL M1B’ V + out M2B’ CC RC Fig.

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